Problem about ISA design
Learning Goal: I’m working on a electrical engineering question and need support to help me learn.
Please see the details in the attachment. (ONLY the Q1)
In this problem you will implement a custom ISA named ISA-MemBound that is designed for workload using a lot of memory
a) Draw the single-cycle microarchitecture of ISA-MemBound that minimizes cycle time using the provided blocks. You must show how all control signals (pseudo code is fine) are generated and appropriately connect them.
b) Assuming all addresses are preloaded in the register file (e.g., in t0, t1, t2), implement the TrplLoadAcc instruction using the least amount of standard MIPS instructions. Assuming the MIPs machine runs at the same frequency, what is the speedup? Using the Iron Law of Performance, where can we say the speedup if coming from?
c)Why stop at 3 loads? If you know how many loads you need to do, you could code them all into a single instruction and indicate, as part of the instruction itself, how many loads each instruction will perform. E.g., Load 5, addr1, addr2, addr3, addr4, addr5 would load 5 data whereas Load 2 addr1, addr2 would only load two. Both are examples of the same Load instruction. What are the pros and cons of encoding different number of loads per instruction
d) You notice that the register file isn’t doing a whole lot, since all data is effectively coming in and out of memory with no reuse. Therefore, you decide to remove it. Alter the ISA to work without a register file by completing the encodings and redefining the instruction semantics. Explain the major changes and assumptions using a few sentences and at least one pro and one con of this design.
Please do not plagiarize
Explicitly list assumptions you make about questions when the information is ambiguous
The instruction formats are provided to remove ambiguity. If you’re unclear, please ask or state you assumption. Assumptions cannot contradict provided definitions.
Requirements: Answer in details